FPGA Based Detector Signal Processing

Course 0000003745 in WS 2016/7

General Data

Course Type Lecture w/ Exercise
Semester Weekly Hours 4 SWS
Organisational Unit Hadronic Structure and Fundamental Symmetries
Lecturers Stephan Paul
Yunpeng Bai
Dominic Gaisbauer
Igor Konorov
Dmytro Levit
Dates Thursday, 14:00–16:00
and 15 dates in groups

Assignment to Modules

Further Information

Courses are together with exams the building blocks for modules. Please keep in mind that information on the contents, learning outcomes and, especially examination conditions are given on the module level only – see section "Assignment to Modules" above.

additional remarks Detector data acquisition and online signal processing with programmable logic / field programmable gate arrays (FPGAs). - Introduction to the FPGA design process (modeling, simulation, synthesis, Xilinx design tools) - Introduction to the VHDL hardware description language (modularity, concurrent/sequential statements, synchronous/asynchronous logic) - Electronic design with VHDL and FPGAs (pipelined data processing, data flow control, counters, state machines) - Signal processing basics (signal sampling, FFT, digital filters) - Detector readout concepts (analog pipeline ASICs, sampling ADCs) - Debug and measurement equipment (oscilloscope, logic analyzer) - Design of a data acquisition system based on Xilinx FPGAs for a particle detector. (frontend ASIC configuration and readout, signal baseline correction, trigger decision, amplitude detection, ...) The course is divided into a lecture part and an applied laboratory part. The basic theory is covered by the lecture which can be applied immediately to the design software in the laboratory part. The different tasks for the final data acquisition project are shared between the students and can be implemented besides the course. The Xilinx FPGA design software is also available for installation on student laptops.
Links E-Learning course (e. g. Moodle)
TUMonline entry

Equivalent Courses (e. g. in other semesters)

SS 2016 FPGA Based Detector Signal Processing Bai, Y. Huber, S. Konorov, I. Levit, D.
Responsible/Coordination: Paul, S.
Thursday, 14:00–16:00
and dates in groups
WS 2015/6 FPGA Based Detector Signal Processing Paul, S.
Assistants: Bai, Y.Huber, S.Konorov, I.Levit, D.
Thursday, 14:00–16:00
WS 2010/1 FPGA based detector signal processing singular or moved dates
and dates in groups
SS 2010 FPGA based detector signal processing singular or moved dates

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