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Master Seminar Resource-Aware Computing (IN2183,IN2107,IN0014)

Course 0000002603 in SS 2015

General Data

Course Type seminar
Semester Weekly Hours 2 SWS
Organisational Unit Informatics 5 - Chair of Scientific Computing (Prof. Bungartz)
Lecturers
Dates

Assignment to Modules

Further Information

Courses are together with exams the building blocks for modules. Please keep in mind that information on the contents, learning outcomes and, especially examination conditions are given on the module level only – see section "Assignment to Modules" above.

additional remarks In the last ten years the period of vast increases in processing power mostly achieved by increasing the clock frequency of a processor has come to an end. Instead, computer architectures are getting more complex in order to accommodate the growing demand for processing power. Modern CPUs typically have a wide range of SIMD instructions for fine-grained data parallelism, and are capable of executing several threads on each of their several cores. Memory accesses are passed through multiple cache levels to hide memory access latencies. In addition to that, hardware specialized in performing massively parallel computations is getting more and more popular. Examples are GPUs and accelerators such as the Xeon Phi. In the HPC context, several nodes, each with its own CPU(s) and GPU(s) may be joined into a cluster. Regular programming techniques and paradigms are no longer sufficient to fully utilize this hardware. Frameworks such as OpenCL take the structure and heterogeneity of the underlying hardware into account and provide the programming environment to expose all available resources, such as GPUs and accelerators. Novel approaches (such as invasive computing) expose the allocation of resources to the users, allowing them to request required resources and, by offering the reallocation of resources at runtime, enabling them to adapt to changing computing demands. The behavior of the hardware at runtime also needs to be considered. Modern Cluster architectures are not necessarily capable to run at peak utilization 100% of the time. To avoid the overheating of the hardware and the resulting degradation of the silicon, the clock frequency of the CPU may be drastically reduced, or single nodes may even be shut down completely for a time. Taking these problems into account is an additional challenge developers face today.
Links TUMonline entry

Equivalent Courses (e. g. in other semesters)

SemesterTitleLecturersDates
SS 2024 M.Sc. Seminar: Modern Trends in High Performance Computing (IN218305, IN2107) Bader, M. Liu Weng, H. Narvaez Rivas, S. Tue, 12:00–14:00, MI 00.08.055
Fri, 12:00–14:00, MI 02.07.023
SS 2023 M.Sc. Seminar: Modern Trends in High Performance Computing (IN218305, IN2107) Bader, M. Dorozhinskii, R. Gratl, F. Mühlhäußer, M. Tue, 10:00–12:00, MI 02.07.023
Fri, 12:00–14:00, MI 02.07.023
SS 2022 M.Sc. Seminar: Modern Trends in High Performance Computing (IN218305, IN2107) Bader, M. Dorozhinskii, R. Narvaez Rivas, S. Tue, 10:00–12:00, MI 02.07.023
Fri, 12:00–14:00, MI 02.07.023
and singular or moved dates
SS 2021 M.Sc. Seminar: Modern Trends in High Performance Computing (IN218305, IN2107) Narvaez Rivas, S. Samfaß, P.
Responsible/Coordination: Bader, M.
Tue, 10:00–12:00, virtuell
Fri, 12:00–14:00, virtuell
and singular or moved dates
SS 2020 Seminar: Future Trends in Computing (IN218305, IN2107) Samfaß, P.
Responsible/Coordination: Bader, M.
SS 2019 Seminar: Future Trends in Computing (IN218305, IN2107) Samfaß, P.
Responsible/Coordination: Bader, M.
SS 2018 Seminar: Future Trends in Computing (IN2183,IN2107,IN0014)
Responsible/Coordination: Bader, M.
SS 2017 Seminar: Future Trends in Computing (IN2183,IN2107,IN0014)
Responsible/Coordination: Bader, M.
SS 2016 Seminar: Future Trends in Computing (IN2183,IN2107,IN0014)
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