System-on-Chip Technologies
Module EI7384
This module handbook serves to describe contents, learning outcome, methods and examination type as well as linking to current dates for courses and module examination in the respective sections.
Module version of SS 2017 (current)
There are historic module descriptions of this module. A module description is valid until replaced by a newer one.
Whether the module’s courses are offered during a specific semester is listed in the section Courses, Learning and Teaching Methods and Literature below.
available module versions | |
---|---|
SS 2017 | WS 2013/4 |
Basic Information
EI7384 is a semester module in English language at Master’s level which is offered in winter semester.
This Module is included in the following catalogues within the study programs in physics.
- Catalogue of non-physics elective courses
Total workload | Contact hours | Credits (ECTS) |
---|---|---|
150 h | 45 h | 5 CP |
Content, Learning Outcome and Preconditions
Content
This course provides basics, current trends and challenges in the development of digital system-on-chip (SoC). We start with the main steps for building arbitrary CMOS-based combinatorial logic and sequential digital data processing and control circuitry (e.g. Finite State Machines) and explaining their role and significance in the scope of key system-on-chip components: microprocessors, memories and interconnects. The microarchitectural structure and building blocks of processor elements (RISC cores), on-/off-chip memory technology (SRAM, DRAM, Flash), bus and point-to-point interconnect standards (Processor Local Bus, Advanced Microcontroller Bus Architecture, FIFO) as well as the design of communications specific arithmetic blocks (adder, multipliers, shift and comparators) will be introduced and analyzed. Finally, we will introduce main implementation methods for SoCs, such as FPGA, standard cell and full custom design, and discuss methods for low power design, which is vital for the development of SoCs in embedded systems.
Learning Outcome
At the end of the module students are able to analyze and evaluate the structure and operation of systems-on-chip, including its main building blocks, e.g. processor, on-/off-chip memories, and interconnect, as well as implementation methods and techniques for low power consumption.
Preconditions
Bachelor courses on semiconductor devices and digital circuits, basics in computer architecture
Courses, Learning and Teaching Methods and Literature
Courses and Schedule
WS 2022/3
WS 2021/2
WS 2020/1
WS 2019/20
WS 2018/9
WS 2017/8
WS 2016/7
WS 2015/6
WS 2014/5
WS 2013/4
WS 2012/3
Type | SWS | Title | Lecturer(s) | Dates | Links |
---|---|---|---|---|---|
VI | 3 | System-on-Chip Technologies |
Biersack, F.
Herkersdorf, A.
Stechele, W.
Wild, T.
Responsible/Coordination: Surhonne, A. |
Thu, 15:00–16:30, 0220 Thu, 09:45–10:30, 1260 and singular or moved dates |
eLearning |
Learning and Teaching Methods
Lecture material is accompanied by corresponding tutorials.
Students will analyze technical publications (as distributed during the course) like data-sheets as representation of building blocks and for usage in own developments of building blocks during the tutorials.
Students will analyze technical publications (as distributed during the course) like data-sheets as representation of building blocks and for usage in own developments of building blocks during the tutorials.
Media
- Presentations
- Lecture notes
- Exercises with solutions as download
- Lecture notes
- Exercises with solutions as download
Literature
- J. Hennessy, "Computer Architecture. A Quantitative Approach", Elsevier
- J. Rabaey, "Digital Integrated Circuits", Prentice Hall
- N. Weste, K. Eshraghian, "Principles of CMOS VLSI Design", Addison Wesley
- J. Rabaey, "Digital Integrated Circuits", Prentice Hall
- N. Weste, K. Eshraghian, "Principles of CMOS VLSI Design", Addison Wesley
Module Exam
Description of exams and course work
The module exam is a written exam (75 min).
Students demonstrate that they have gained both fundamental and deeper understanding in various aspects of System on Chip Technologies and their analysis, from combinatorial logic to complete Embedded Systems. They have to answer the questions with self-formulated responses, checking boxes of multiple choice questions, sketch circuit or qualitative performance diagrams and do quantitative calculations. The allowed support material is constraint to a single sheet, individually prepared reminder notice.
Students demonstrate that they have gained both fundamental and deeper understanding in various aspects of System on Chip Technologies and their analysis, from combinatorial logic to complete Embedded Systems. They have to answer the questions with self-formulated responses, checking boxes of multiple choice questions, sketch circuit or qualitative performance diagrams and do quantitative calculations. The allowed support material is constraint to a single sheet, individually prepared reminder notice.
Exam Repetition
There is a possibility to take the exam in the following semester.