This module handbook serves to describe contents, learning outcome, methods and examination type as well as linking to current dates for courses and module examination in the respective sections.
EI5003 is a semester module in English language at Master’s level which is offered in winter semester.
This module description is valid to SS 2012.
|Total workload||Contact hours||Credits (ECTS)|
|90 h||45 h||3 CP|
Content, Learning Outcome and Preconditions
From MOSFET transistors to the realization of combinatorial/sequential logic, Finite State Machines (FSM), SRAM, DRAM, Flash, FPGA
IC design platforms: FPGA, standard cell, full custom design, SoC (System-on-Chip)
Timing, power, area estimation and optimization, clock distribution
Packaging and I/O technology
Courses, Learning and Teaching Methods and Literature
Learning and Teaching Methods
In addition to the individual methods of the students consolidated knowledge is aspired by repeated lessons in exercises and tutorials.
During the lectures students are instructed in a teacher-centered style. The exercises are held in a student-centered way.
- Lecture notes
- Exercises with solutions as download
- J. Hennessy "Comp. Architecture-A Quantit.Approach"
- J. Rabaey, "Digital Integrated Circuits", Prentice Hall
- N. Weste, K. Eshraghian, "Principles of CMOS VLSI Design", Addison Wesley